1. Field of the Invention
The present invention relates to a shift register circuit and more particularly, to a shift register circuit used in such as a scan line drive circuit in an image display and comprising only the same conductivity type field effect transistor.
2. Description of the Background Art
According to an image display such a liquid crystal display (referred to as the “display” hereinafter), a gate line (scan line) is provided with respect to each pixel row (pixel line) of a display panel in which a plurality of pixels are arranged like a matrix, and the display image is updated by sequentially selecting and driving the gate line every cycle of one horizontal period of a display signal. Thus, as a gate line drive circuit (scan line drive circuit) for sequentially selecting and driving the pixel line, that is, the gate line, a shift register that makes one round of shifting for one frame period of the display signal can be used.
It is preferable that the shift register used in the gate line drive circuit comprises only the same conductivity type field effect transistor in order to reduce the steps in the manufacturing process of the display. Therefore, various kinds of shift registers comprising only an N-type or P-type field effect transistor and displays mounting it have been proposed (in Japanese Patent Application Laid Open No. 10-500243, for example). The field effect transistor includes an MOS (Metal Oxide Semiconductor) transistor, a TFT (Thin Film Transistor) and the like.
In addition, the shift register as the gate line drive circuit is constituted such that a plurality of cascade-connected shift register circuits are provided with respect to each pixel line, that is, each gate line. According to this specification, each of the plurality of shift register circuits that constitute the gate line drive circuit is referred to as the “unit shift register” for simplification of the description.
Japanese Patent Application Laid-Open No. 10-500243 discloses a unit shift register constituted such that the number of transistors in a circuit is decreased as compared with a conventional one (FIG. 2 in Japanese Patent Application Laid-Open No. 10-500243, for example). According to the unit shift register (refer to FIG. 3 in this specification), a first transistor (Q1) is provided as an output pull-up transistor connected between a first clock terminal (CK1) to which a predetermined first clock signal is inputted and an output terminal (OUT). The first transistor is turned on in response to a predetermined input signal (Gn−1) and turned off in response to a predetermined reset signal (Gn−1). Thus, the output signal (Gn) of the unit shift register is outputted when the first transistor is turned on by the input signal and the first clock signal is transmitted to the output terminal.
Meanwhile, in a period the unit shift register does not output the output signal, the first transistor is kept in an off state so that the first clock signal is not transmitted to the output terminal. Thus, the input signal is not inputted in that period. However, in fact, when the first clock signal is inputted when the first transistor is in the off state, the gate potential of the first transistor tries to rise due to the coupling through the overlap capacity between the gate and drain of the first transistor. Thus, when the gate potential exceeds the threshold voltage of the first transistor, the first transistor to be kept in the off state is unnecessarily turned on, which causes a defective operation of the unit shift register.
According to the unit shift register in Japanese Patent Application Laid-Open No. 10-500243, a second clock signal (/CLK) that is a complementarity signal of the first clock signal is applied to the gate of the first transistor through a first capacity element (C2) in order to prevent the defective operation. That is, the variation in the gate potential of the first transistor caused by the first clock signal can be offset by the second clock signal, so that the gate potential is prevented from rising.
Meanwhile, when the unit shift register outputs the output signal, the output terminal, that is, the source of the first transistor rises and becomes H (High) level. Therefore, when it is assumed that the gate potential of the first transistor is constant, the voltage between the gate and source of the first transistor is lowered while the output signal is outputted and the drive capability (current flowing capability) is lowered. In this case, the problem is that the rising and falling speeds of the output signal are lowered and it is difficult to implement the high-speed operation. Especially, since it is necessary to charge the gate line at high speed to activate it in order to ensure sufficient writing time of data to the pixel, in the gate line drive circuit of the display, lowering in the drive capability of the first transistor, that is, lowering in the drive capability of the unit shift register becomes a big problem.
Thus, according to the unit shift register in Japanese Patent Application Laid-Open No. 10-500243, a second capacity element (C1) is further provided between the output terminal and the gate of the first transistor, so that the gate of the first transistor rises in voltage due to the coupling through the second capacity element at the time of outputting the output signal. That is, even when the potential of the output terminal rises, since the gate potential of the first transistor also rises, the voltage between the gate and source of the first transistor can be highly kept. Therefore, there is an effect that the drive capability of the first transistor can be prevented from being lowered when the output signal is outputted.
However, according to the unit shift register in Japanese Patent Application Laid-Open No. 10-500243, as described above, the first capacity element (C2) for preventing the gate potential from rising due to the first clock signal (CLK) is connected to the gate of the first transistor (Q1). Since the first capacity element functions to prevent the variation in the gate potential of the first transistor when the output signal is outputted also, the rising action of the gate of the first transistor by the second capacity element (C1) is also prevented. That is, the effect of the second capacity element (C1) that prevents the drive capability of the first transistor from being lowered at the time of outputting the output signal is weakened by the first capacity element (C2). As a result, when the drive capability of the first transistor is not sufficiently ensured, the problem the high speed operation is difficult arises again.
As described above, according to the unit shift register in Japanese Patent Application Laid-Open No. 10-500243, the first capacity element that prevents the defective operation while the output signal is not outputted results in weakening the effect of the second capacity element that the drive capability of the shift register can be ensured while the output signal is outputted, so that it is said that the two operations are in antinomy relation.